1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a multi-chip package type semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate.
2. Description of Related Art
Various multi-chip package type semiconductor devices are already known.
By way of illustration, JP-A 2002-110898 (which will be also called Patent Document 1 and which corresponds to U.S. Pat. No. 7,115,977) discloses a semiconductor device comprising a substrate having a surface on which a wiring pattern is formed; a first semiconductor element (a first semiconductor chip), mounted on the substrate, having first electrode pads; a second semiconductor element (a second semiconductor chip) mounted on the first semiconductor element (the first semiconductor chip), having second electrode pads; first wires connecting a first area of the first electrode pads with the second electrode pads; and second wires connecting a second area of the first electrode pads expect for the first area with the wiring pattern. That is, the semiconductor device disclosed in Patent Document 1 comprises a multi-chip package (MCP) type semiconductor device in which a plurality of semiconductor chips are equipped.
However, the semiconductor device disclosed in Patent Document 1 involves problems as follows.
In recent years, according to demands for reduction in size of potable devices or the like, semiconductor chips in which sizes of chips and sizes of electrode pads are downsized are currently on the market. Therefore, in an MCP type semiconductor device in which a plurality of semiconductor chips are assembled, the plurality of semiconductor chips having different sizes of electrode pads may be mixed in the same package.
In this event, there is a fear that bonding cannot be favorably carried out to smaller electrode pads if wires having large diameters suited to large electrode pads are used. If wires having small diameters suited to small electrode pads are used, the wires become easily deformed on molding, and a wire short-circuit of a wire flow have become increasingly risky.
In addition, JP-A 2011-71317 (which will be also called Patent Document 2 and which corresponds to US 2011/0074019A1) discloses technique for preventing interference between a wide width part of a wire and an insulating film around electrode pads by forming, on the electrode pad, a bump having a width narrower than the wide width part of the wire and by connecting the wide width part of the wire via the bump.
The semiconductor device disclosed in Patent Document 2 involves problems as follows.
Although Patent Document 2 describes configuration so as to arrange the wide width parts of the wires in a staggered manner, Patent Document 2 does not consider the MCP type semiconductor device in which a plurality of semiconductor chips having different sizes of electrode pads are assembled. Accordingly, there is a limit to connect the wide width parts of the wires with the electrode pads which have small pad sizes and which are arranged at a narrow pitch and there still remains the risk of the wire short-circuit due to flow of resin on molding.